A technique is known in which, to form a thin LSI chip layer, an integrated circuit or the like is formed on a silicon substrate and thereafter formed thin by a grinder from the lower surface side of the substrate. The integrated circuit or the like is formed only on the upper surface of the silicon substrate, and most of the region of the substrate is ground and wasted. With this technique, the resources cannot be used effectively.
As the semiconductor devices shrink in feature size and their integration density increases, the quantity of heat generated by a chip is expected to increase remarkably. Accordingly, to establish a technique for making a thin LSI chip layer is sought for. As an ordinary semiconductor chip lacks flexibility, when it is to be mounted on a thin device such as an IC card, its bending strength must be high. This is because if the ordinary semiconductor chip is to be carried like an IC card, a bending stress sometimes acts on the semiconductor device when putting away the IC card or the like. Accordingly, the LSI chip or the like to be mounted on the thin device also must form a thin layer from the viewpoint of heat radiation and flexibility. As a technique for forming a thin-film semiconductor device, the following ones are disclosed.
According to the thin film forming technique disclosed in Japanese Patent Laid-Open No. 9-312349 (FIGS. 2 to 4), a device is formed on a semiconductor layer formed on the upper surface of a porous layer. The semiconductor layer on which the device is formed is split at the porous layer to form a thin-film semiconductor device or IC card.
According to the thin film forming technique disclosed in Japanese Patent Laid-Open No. 2000-349066 (FIG. 1), the periphery of a semiconductor layer formed on the upper surface of a porous layer is removed so that, when a semiconductor substrate is to be split at the porous layer, cracking does not occur easily.
According to the thin film forming technique disclosed in Japanese Patent Laid-Open No. 2001-284622 (FIGS. 3 and 4), a region where a porous layer is not to be formed is provided on a semiconductor substrate. This prevents a semiconductor layer formed on the surface of a porous material from splitting before it is transferred to a support member side. When the porous layer is exposed to the periphery of the semiconductor substrate, the exposed porous layer is removed.
According to the thin film forming technique disclosed in Japanese Patent Laid-Open No. 2002-141327 (FIGS. 1 to 3), the first porous layer is formed with the first current density on a region, other than the periphery, of the upper surface of a semiconductor substrate. After that, the second porous layer is formed with the second current density on the entire upper surface of the semiconductor surface. Then, a crystal thin film is formed on the region, other than the periphery, of the upper surface of the semiconductor substrate.
According to the conventional thin film forming techniques, one or a plurality of circuit elements are formed on the semiconductor substrate while the porous layer serving as a separation region is exposed. In the circuit element forming step (to be referred to as the “device forming step” hereinafter), the semiconductor substrate may undesirably peel off.
For example, in the invention described in Japanese Patent Laid-Open No. 9-312349 (FIGS. 2 to 4), in the step of forming the device on the semiconductor layer, the periphery of the porous layer is exposed, so that when, e.g., the substrate is to be arranged in an apparatus or transported, the periphery of the substrate may come into contact with the apparatus or a transport member so the semiconductor layer may come off from the porous layer formed in the periphery of the substrate.
In the invention described in Japanese Patent Laid-Open No. 2000-349066 (FIG. 1), the periphery of the porous layer is left exposed since the porous layer is formed until the semiconductor layer is split at the porous layer. Therefore, in the same manner as in Japanese Patent Laid-Open No. 9-312349 (FIGS. 2 to 4), the semiconductor layer may peel off from the exposed porous layer.
In the invention described in Japanese Patent Laid-Open No. 2001-284622 (FIGS. 3 and 4), as the region where the porous layer is not to be formed is provided, the semiconductor layer does not split easily. However, the periphery of the porous layer is left exposed since the porous layer is formed until the semiconductor layer is separated at the porous layer. Therefore, in the same manner as in Japanese Patent Laid-Open No. 9-312349 (FIGS. 2 to 4), the semiconductor layer may peel off from the exposed porous layer.
In the invention described in Japanese Patent Laid-Open No. 2002-141327 (FIGS. 1 to 3), the second porous layer is left exposed since the second porous layer is formed and until the semiconductor layer is split at the first porous layer. Therefore, in the same manner as in the above patent references, the crystal thin film may peel off from the second porous layer formed in the periphery of the substrate.
In this manner, with the prior art, the porous layer is exposed, so that when, e.g., the substrate is to be arranged in an apparatus or transported, the periphery of the substrate may come into contact with the apparatus or a transport member, and unexpected peel-off occurs from the porous layer formed in the periphery of the substrate. If the semiconductor layer peels in the device forming step, the peeled piece may drop onto another semiconductor substrate to cause defective operation of a device located where the peeled piece has dropped, and consequently the chip yield can decrease. If the semiconductor substrate peels, to remove the peeled piece completely, the manufacturing apparatus must be stopped and the components in the apparatus must be cleaned. This decreases the operation efficiency of the device forming step and leads to the need for maintenance steps, thus adversely affecting device formation.